module ClockDivider (

	input CLK_50MHz, 		//50MHz clock input
	input rst_n, 			//Active-LOW reset signal
	
	output CLK_100Hz,	 	//100Hz clock; You can tweak the output type accordingly.
	output CLK_1Hz			//1Hz clock; You can tweak the output type accordingly.
);

	wire [27:0] count_1Hz;
	wire [27:0] count_100Hz;
	wire match_1Hz;
	wire match_100Hz;
	wire match_1Hz_latched;
	wire match_100Hz_latched;
	wire enable_count1Hz;
	wire enable_count100Hz;

	Counter28bit counter_1Hz (
		.clk(CLK_50MHz),
		.rst_n(enable_count1Hz),
		.Q(count_1Hz)
	);

	Counter28bit counter_100Hz (
		.clk(CLK_50MHz),
		.rst_n(enable_count100Hz),
		.Q(count_100Hz)
	);

	assign match_1Hz = (count_1Hz == 28'd24999999);
	assign match_100Hz = (count_100Hz == 28'd249999);
	// use for test
	//assign match_1Hz = (count_1Hz == 28'd2499);
	//assign match_100Hz = (count_100Hz == 28'd24); 
	
	

	MyDFF latch_match1 (
		.clk(CLK_50MHz),
		.rst_n(rst_n),
		.D(match_1Hz),
		.Q_out(match_1Hz_latched)
	);

	MyDFF latch_match100 (
		.clk(CLK_50MHz),
		.rst_n(rst_n),
		.D(match_100Hz),
		.Q_out(match_100Hz_latched)
	);

	assign enable_count1Hz = rst_n & ~match_1Hz_latched;
	assign enable_count100Hz = rst_n & ~match_100Hz_latched;

	wire q1_d, q1_q;
	wire q100_d, q100_q;

	xor(q1_d, match_1Hz, q1_q);
	xor(q100_d, match_100Hz, q100_q);

	MyDFF dff_1Hz (
		.clk(CLK_50MHz),
		.rst_n(rst_n),
		.D(q1_d),
		.Q_out(q1_q)
	);

	MyDFF dff_100Hz (
		.clk(CLK_50MHz),
		.rst_n(rst_n),
		.D(q100_d),
		.Q_out(q100_q)
	);

	assign CLK_1Hz = q1_q;
	assign CLK_100Hz = q100_q;

endmodule